The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2021
Filed:
Nov. 20, 2018
Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Wuhan, CN;
Xue Li, Wuhan, CN;
Abstract
A test circuit layout structure for a display panel is disclosed and includes a chip on film (COF) bonding region having two ends connected to two power conductor regions extending toward an active area; a test circuit region located between the COF bonding region and the two power conductor regions; two test pad regions and two electrostatic protection regions are both distributed around two sides of the COF bonding region; wherein a plurality of wires extend from the test pad regions and are configured to couple the electrostatic protection regions, the COF bonding region, and the test circuit region; wherein resistivity of the wires and resistivity of the power conductor regions are the same; and wherein the wires bypass the power conductor regions disposed in the same layer as the wires, alternatively, the wires and the power conductor regions are overlapped in an insulation manner.