The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Feb. 28, 2018
Applicant:

Osram Opto Semiconductors Gmbh, Regensburg, DE;

Inventors:

Mathias Wendt, Hausen, DE;

Klaus Müller, Pettendorf, DE;

Laurent Tomasini, Reutte, AT;

Assignee:

OSRAM OLED GmbH, Regensburg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 33/00 (2010.01); H01S 5/0237 (2021.01); H01L 23/48 (2006.01); B23K 1/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49866 (2013.01);
Abstract

A method of attaching a semiconductor chip to a lead frame, including A) providing a semiconductor chip, B) applying a solder metal layer sequence on the semiconductor chip, C) providing a lead frame, D) applying a metallization layer sequence on the lead frame, E) applying the semiconductor chip on the lead frame via the solder metal layer sequence and the metallization layer sequence, and F) heating the arrangement produced under E) to attach the semiconductor chip to the lead frame, wherein the solder metal layer sequence includes a first metallic layer including an indium-tin alloy, a barrier layer arranged above the first metallic layer, and a second metallic layer including gold arranged between the barrier layer and the semiconductor chip.


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