The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Jun. 17, 2020
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Dor Marom, Kfar-Saba, IL;

Shai Baron, Ramat-Hasharon, IL;

Gadi Vishne, Petach-Tikva, IL;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/04 (2006.01); G11C 7/10 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G11C 7/04 (2013.01); G06F 13/1689 (2013.01); G11C 7/1072 (2013.01); G11C 7/1078 (2013.01); G11C 2207/2254 (2013.01);
Abstract

The present disclosure generally relates to calibrating the communication with a memory device. To ensure proper calibration, interface training (IFT) needs to occur. IFT involves aligning the sampling point, which is an inflection point, of a clock signal with a data signal. The sampling point of the clock (i.e., the clock edge) needs to be located within the valid window of the data signal. The valid window of the data signal is the time in which the signal is guaranteed to be stable, i.e., after the signal has finished the signal transition time. If the sampling point is aligned with the inflection point of the data signal, then the data signal is not properly aligned. If the sampling point is aligned with the rising or falling edge of the data signal, the data may be obtained, but the data signal is misaligned and is dangerously close to being unreadable. To ensure properly aligning of the clock signal with the data signal, either additional clock signals or a faster clock signal can be used to ensure that misaligned data signals are identified and then properly aligned.


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