The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Nov. 27, 2019
Applicant:

Himax Technologies Limited, Tainan, TW;

Inventors:

Yu-Feng Yen, Tainan, TW;

Yin-Tung Lu, Tainan, TW;

Chih-Yu Chuang, Tainan, TW;

Han-Yi Kuo, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01); G01N 27/22 (2006.01); G01N 27/24 (2006.01); G02F 1/133 (2006.01); G02F 1/1335 (2006.01); H04N 5/225 (2006.01);
U.S. Cl.
CPC ...
G06K 9/00255 (2013.01); G01N 27/228 (2013.01); G01N 27/24 (2013.01); G02F 1/13306 (2013.01); G02F 1/133504 (2013.01); H04N 5/2256 (2013.01); G02F 2203/03 (2013.01);
Abstract

An optical film stack including a DOE, a first detecting circuit layer, a liquid crystal changeable diffuser, and a conductive structure is provided. The first detecting circuit layer is disposed on the DOE. The liquid crystal changeable diffuser is disposed beside the DOE and includes a first transparent substrate, a second detecting circuit layer, a second transparent substrate, a third detecting circuit layer, and a liquid crystal layer. The second detecting circuit layer is disposed on the first transparent substrate. The second transparent substrate is disposed beside the first transparent substrate. The third detecting circuit layer is disposed on the second transparent substrate. The liquid crystal layer is disposed between the first transparent substrate and the second transparent substrate. The conductive structure electrically connects the first detecting circuit layer, the second detecting circuit layer, and the third detecting circuit layer.


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