The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Apr. 18, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyung-bong Kim, Hwaseong-si, KR;

Min-su Kim, Hwaseong-si, KR;

Dae-seong Lee, Busan, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); G06F 30/392 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01); H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); G06F 2119/18 (2020.01);
Abstract

An integrated circuit including standard cells, a method and a computing system for designing and fabricating the same are provided. A computer-implemented method involves placing, based on a standard cell library, standard cells of an integrated circuit to be fabricated, and routing the placed standard cells. A position of a first wiring of a placed cell among the placed standard cells may be adjusted based on a position of a second wiring used for the routing. The first wiring is provided from at least one standard cell, formed in a same layer as that of the second wiring, and spaced from the second wiring in a first direction. An integrated circuit layout having the adjusted position of the first wiring, is produced.


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