The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Sep. 15, 2020
Applicant:

Rdc Semiconductor Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Ching Tseng, Hsinchu, TW;

Ching-Chong Chuang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); G06F 1/10 (2006.01); H03K 3/037 (2006.01); G06F 1/12 (2006.01); G06F 1/06 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 1/06 (2013.01); G06F 1/12 (2013.01); H03K 3/037 (2013.01); H03K 5/00 (2013.01); H03K 2005/00078 (2013.01);
Abstract

An integrated circuit includes a first stage and a second stage. The first stage receives a previous stage output data and a clock signal and generates a first output data. The second stage receives the first output data and the clock signal. The first stage includes a first flip-flop circuit, a first static combinational circuit, a dynamic combinational circuit and a multi-phase generator. The first flip-flop circuit receives the previous output data and the clock signal and generates an input data. The first static combinational circuit receives the input data and generates an intermediate data. The multi-phase generator receives the clock signal and generates a delayed clock signal. The dynamic combinational circuit receives the intermediate data and the delayed clock signal and generates the first output data.


Find Patent Forward Citations

Loading…