The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Sep. 05, 2019
Applicant:

Zopoise Technology (Zhuzhou) Co., Ltd., Zhuzhou, CN;

Inventors:

Bruce Pi, Zhuzhou, CN;

Wei Kang, Zhuzhou, CN;

Jie Dong, Zhuzhou, CN;

Weixiong Liu, Zhuzhou, CN;

Guicheng Yin, Zhuzhou, CN;

Zhibin Zhang, Zhuzhou, CN;

Yikai Xu, Zhuzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); F21V 29/503 (2015.01); F21V 29/70 (2015.01); F21V 29/85 (2015.01); F21V 3/00 (2015.01); F21V 7/05 (2006.01); H05K 1/03 (2006.01); H05K 1/09 (2006.01); H05K 3/00 (2006.01); H05K 3/12 (2006.01); H05K 3/28 (2006.01); F21Y 115/10 (2016.01);
U.S. Cl.
CPC ...
H05K 1/0271 (2013.01); F21V 3/00 (2013.01); F21V 7/05 (2013.01); F21V 29/503 (2015.01); F21V 29/70 (2015.01); F21V 29/86 (2015.01); H05K 1/0204 (2013.01); H05K 1/0216 (2013.01); H05K 1/0266 (2013.01); H05K 1/0274 (2013.01); H05K 1/0306 (2013.01); H05K 1/09 (2013.01); H05K 3/0052 (2013.01); H05K 3/1216 (2013.01); H05K 3/1283 (2013.01); H05K 3/28 (2013.01); F21Y 2115/10 (2016.08); H05K 2201/09936 (2013.01); H05K 2201/10106 (2013.01); H05K 2201/10113 (2013.01); H05K 2203/1131 (2013.01);
Abstract

The present disclosure provides a PCB board, a manufacturing method of a PCB board, and an electrical device, where the PCB board includes an insulating dielectric layer which is a glass substrate layer including a top surface and a bottom surface disposed oppositely; a conductive wiring layer which is disposed on a top surface of the insulating dielectric layer; and a top ink layer which is coated on the conductive wiring layer. According to the technical solution provided by the embodiment of the disclosure, the PCB board does not generate the phenomenon of deformation warping, and the conductive wiring layer is not easily peeled off from the insulating medium layer, and the use performance of the PCB board is good.


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