The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Jul. 20, 2020
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Chan-Hsiang Weng, Hsinchu, TW;

Hung-Yi Hsieh, Hsinchu, TW;

Tzu-An Wei, Hsinchu, TW;

Ting-Yang Wang, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/80 (2006.01); H03M 1/06 (2006.01); H03M 1/08 (2006.01); H03M 1/12 (2006.01); H03M 1/38 (2006.01);
U.S. Cl.
CPC ...
H03M 1/802 (2013.01); H03M 1/0656 (2013.01); H03M 1/0854 (2013.01); H03M 1/121 (2013.01); H03M 1/38 (2013.01);
Abstract

The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.


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