The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2021
Filed:
Aug. 12, 2020
Applicant:
Analog Devices International Unlimited Company, Limerick, IE;
Inventor:
Roberto Sergio Matteo Maurino, Turin, IT;
Assignee:
Analog Devices International Unlimited Company, Limerick, IE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 3/00 (2006.01); H03M 1/20 (2006.01); H03M 1/12 (2006.01); H03M 1/06 (2006.01); H03M 1/18 (2006.01); H03M 1/50 (2006.01);
U.S. Cl.
CPC ...
H03M 1/201 (2013.01); H03M 1/0626 (2013.01); H03M 1/0668 (2013.01); H03M 1/122 (2013.01); H03M 1/186 (2013.01); H03M 1/504 (2013.01);
Abstract
Techniques to implement subtractive dither in a multi-stage ADC. Subtractive dither involves adding a first dither signal at a first node and adding a second dither signal at a second node (which can be the same as the first node), where the first and second dither signal combine and sum to approximately zero. By utilizing subtractive dither in a multi-stage ADC, the headroom requirements of a loop filter in a main loop of the ADC and the range requirements of a feedback DAC in the main loop can both be relaxed.