The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Jul. 12, 2017
Applicant:

Sakai Display Products Corporation, Sakai, JP;

Inventors:

Shigeru Ishida, Sakai, JP;

Tomohiro Inoue, Sakai, JP;

Ryohei Takakura, Sakai, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 27/1222 (2013.01); H01L 29/66765 (2013.01); H01L 29/78618 (2013.01);
Abstract

A semiconductor device includes a thin film transistor including: a substrate; a gate electrodesupported on the substrate; a semiconductor layerprovided on the gate electrode with a gate insulating layertherebetween, wherein the semiconductor layer includes a first region Rs, a second region Rd, and a source-drain interval region SG that is located between the first region and the second region and overlaps with the gate electrode as seen from a direction normal to the substrate; a first contact layer Cs in contact with the first region and a second contact layer Cd in contact with the second region; a source electrodeelectrically connected to the first region with the first contact layer therebetween; and a drain electrodeelectrically connected to the second region with the second contact layer therebetween, wherein: the semiconductor layer includes a crystalline silicon region, and at least a portion of the crystalline silicon region is located in the source-drain interval region SG; and the semiconductor layer has at least one opening P that is located in the source-drain interval region SG and reaches the gate insulating layer.


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