The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2021
Filed:
Mar. 06, 2020
Applicant:
Qromis, Inc., Santa Clara, CA (US);
Inventors:
Vladimir Odnoblyudov, Danville, CA (US);
Cem Basceri, Los Gatos, CA (US);
Ozgur Aktas, Santa Clara, CA (US);
Assignee:
QROMIS, INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 23/373 (2006.01); H01L 23/66 (2006.01); H01L 29/40 (2006.01); H01L 21/762 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 23/48 (2006.01); H01L 29/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 21/0245 (2013.01); H01L 21/0254 (2013.01); H01L 21/02389 (2013.01); H01L 21/02488 (2013.01); H01L 21/02491 (2013.01); H01L 21/02505 (2013.01); H01L 21/76251 (2013.01); H01L 23/3735 (2013.01); H01L 23/66 (2013.01); H01L 29/404 (2013.01); H01L 29/41766 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 23/481 (2013.01); H01L 29/122 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6627 (2013.01);
Abstract
A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer.