The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Jan. 29, 2019
Applicants:

Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Lei Yan, Beijing, CN;

Feng Li, Beijing, CN;

Yezhou Fang, Beijing, CN;

Jun Fan, Beijing, CN;

Lei Li, Beijing, CN;

Yanyan Meng, Beijing, CN;

Lei Yao, Beijing, CN;

Jinjin Xue, Beijing, CN;

Chenglong Wang, Beijing, CN;

Jinfeng Wang, Beijing, CN;

Lin Hou, Beijing, CN;

Zhixuan Guo, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41733 (2013.01); H01L 29/66757 (2013.01); H01L 29/78618 (2013.01); H01L 29/78633 (2013.01); G02F 1/134363 (2013.01); G02F 1/136227 (2013.01); H01L 27/124 (2013.01); H01L 27/3248 (2013.01);
Abstract

The present disclosure provides a thin film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor includes: an active layer located on one side of the substrate; a first interlayer dielectric layer located on one side of the active layer away from the substrate; a source penetrating through the first interlayer dielectric layer, and connected to the active layer; a second interlayer dielectric layer located on one side of the first interlayer dielectric layer away from the active layer and covering the source; and a drain, wherein the drain comprises a first portion penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.


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