Variable resistance memory devices

Abstract

A variable resistance memory device may include a plurality of stacked structures. Each of the stacked structures may be formed on a substrate, and may include a lower electrode, a variable resistance pattern and a selection pattern sequentially stacked. A threshold voltage control pattern may be formed on the stacked structures, may extend in a second direction parallel to an upper surface of the substrate and may be configured to either increase or decrease a threshold voltage of each selection pattern. An upper electrode may be formed on the threshold voltage control pattern and may extend in the second direction. A first conductive line may contact respective lower surfaces of the lower electrodes of the stacked structures and extend in a first direction perpendicular to the second direction. A second conductive line may contact an upper surface of the upper electrode and extend in the second direction.