The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Apr. 15, 2020
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Te-Yin Chen, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10855 (2013.01); H01L 21/7687 (2013.01); H01L 21/76889 (2013.01); H01L 21/76897 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01);
Abstract

The present application discloses a semiconductor device with a self-aligned landing pad and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a self-aligned landing pad disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The self-aligned landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.


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