The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Nov. 11, 2019
Applicant:

AU Optronics Corporation, Hsin-Chu, TW;

Inventors:

Er-Lang Deng, Hsin-Chu, TW;

Yuan-Nan Chiu, Hsin-Chu, TW;

Chih-Yuan Wu, Hsin-Chu, TW;

Yu-Lin Huang, Hsin-Chu, TW;

I-Sheng Lin, Hsin-Chu, TW;

Kuo-Ting Yang, Hsin-Chu, TW;

Assignee:

AU OPTRONICS CORPORATION, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G11C 19/28 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G11C 19/287 (2013.01); G09G 3/20 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01);
Abstract

A gate driving circuit comprises a plurality of shift registers coupled in serial. An nth shift register includes a driving circuit, a pull-up circuit and a first auxiliary voltage regulator circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a clock signal and output a gate signal according to the clock signal. The pull-up circuit is electrically coupled to the driving circuit. The first auxiliary voltage regulator circuit is electrically coupled to the pull-up circuit and a second node. The first auxiliary voltage regulator circuit is configured to receive a control signal and the second node corresponding to a second voltage.


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