The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Mar. 24, 2020
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Koichi Takeda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/408 (2006.01); G11C 16/02 (2006.01); G11C 16/26 (2006.01); G11C 16/28 (2006.01); G11C 16/24 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 7/12 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 16/02 (2013.01); G11C 16/0408 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/28 (2013.01);
Abstract

A semiconductor device capable of enlarging a read margin of a memory cell and a method of surrounding a read of a memory are provided. The reference word line RWL is activated in a time division manner with respect to the plurality of word lines WL. The precharge circuit PRE applies the read potential VRD to the bit line BL, and the precharge circuit PRE flows the read current Icel from the selected memory cell MC and the read reference current Iref from the reference cell RC to the bit line BL in a time division manner. A detection currents Ird, Irr, each of which is a current proportional to the current flowing through the bitline BL, flows through the current detection line CDL.


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