The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Jul. 03, 2020
Applicant:

AU Optronics Corporation, Hsin-Chu, TW;

Inventors:

Chia-En Wu, Hsin-Chu, TW;

Ming-Hsien Lee, Hsin-Chu, TW;

Wei-Chia Chiu, Hsin-Chu, TW;

Kuan-Yu Chen, Hsin-Chu, TW;

Assignee:

AU OPTRONICS CORPORATION, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2016.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 3/32 (2013.01); G09G 3/2003 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2320/0233 (2013.01);
Abstract

A pixel circuit including a driving transistor, a light emission element, a compensation circuit, a storage capacitor, and a writing circuit is provided. The light emission control circuit is configured to selectively conduct the light emission element to the driving transistor. The compensation circuit is coupled with the light emission control circuit and a control terminal of the driving transistor, and is configured to form a diode-connected structure with the driving transistor. The storage capacitor includes a first terminal and a second terminal. The first terminal of the storage capacitor is coupled with the control terminal of the driving transistor, and the light emission control circuit is configured to selectively conduct the second terminal of the storage capacitor to a first power terminal. The writing circuit is configured to provide different voltages to the first terminal of the storage capacitor and the second terminal of the storage capacitor.


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