The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Sep. 03, 2020
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventor:

Tetsu Hasegawa, Yokohama Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 30/3308 (2020.01); G06F 30/398 (2020.01); G06F 11/00 (2006.01); H03K 19/00 (2006.01); H01L 25/00 (2006.01); G01R 31/28 (2006.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/333 (2020.01); H01L 25/00 (2013.01); H03K 19/00 (2013.01); G01R 31/28 (2013.01); G06F 11/00 (2013.01); G06F 30/3308 (2020.01); G06F 30/398 (2020.01); G06F 2119/02 (2020.01);
Abstract

According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including: a first scan chain and a second scan chain; a clock generator; and a test control circuit. The first scan chain includes: a first flip-flop having a first scan data input terminal and a first output terminal; and a first multiplexer. The first multiplexer is configured to electrically couple the first scan data input terminal to the first output terminal based on a first signal received from the test control circuit to form a first closed loop. The second scan chain includes a second flip-flop having a second scan data input terminal and a third output terminal that is not coupled to the second scan data input terminal.


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