The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Apr. 03, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventor:

Burkhard Steinmacher-Burow, Esslingen Am Neckar, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0817 (2016.01); G06F 12/084 (2016.01); G06F 12/0831 (2016.01); G06F 9/52 (2006.01); G06F 9/54 (2006.01); G06F 12/0808 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0828 (2013.01); G06F 9/522 (2013.01); G06F 9/544 (2013.01); G06F 12/084 (2013.01); G06F 12/0808 (2013.01); G06F 12/0822 (2013.01); G06F 12/0833 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/621 (2013.01);
Abstract

The invention relates to a method for coordinating an execution of an instruction sequence by a processor device of a coherent shared memory system. An instruction is executed and causes the processor device to fill a copy of a memory line to a processor cache memory. The memory line is flagged by the processor device upon detection of first flag information which indicates that propagation of memory coherence across the shared memory system in respect of the memory line is unconfirmed. The memory line is unflagged by the processor device upon detection of second flag information which indicates that the propagation of memory coherence in respect of the memory line is confirmed. Upon execution of a memory barrier instruction, a completion of execution of the memory barrier instruction is prevented while the memory line is flagged.


Find Patent Forward Citations

Steinmacher-Burow, Burkhard. (2021). Coordination of cache memory operations (U.S. Patent No. 11119927). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11119927

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…