The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Sep. 18, 2013
Applicants:

Dipak K Sikdar, Santa Clara, CA (US);

Rajesh Chopra, San Ramon, CA (US);

Inventors:

Dipak K Sikdar, Santa Clara, CA (US);

Rajesh Chopra, San Ramon, CA (US);

Assignee:

MOSYS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 29/44 (2006.01); G11C 29/42 (2006.01); G06F 11/20 (2006.01); G11C 29/06 (2006.01); G11C 29/12 (2006.01); G11C 29/50 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/108 (2013.01); G06F 11/106 (2013.01); G06F 11/2094 (2013.01); G11C 29/06 (2013.01); G11C 29/12 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/4401 (2013.01); G11C 29/50 (2013.01); G11C 29/808 (2013.01);
Abstract

An integrated circuit (IC) chip for transparent and in-service or production repair of single to multiple memory cell defects in a word during the datapath transit of the word between core memory to the interface of the IC via capturing an accurate bit from a word during a write access to a known defective memory address, and by substituting in a non-defective bit into the word during a read access from a known defective memory address. The IC includes: address matching circuit (CAM), a random access memory (RAM) of substitute memory cells containing accurate associated bit data and bit location in word of defect, and data selection circuitry (MUXs) coupled together.


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