The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Dec. 11, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Derek E. Williams, Round Rock, TX (US);

Guy L. Guthrie, Austin, TX (US);

Hugh Shen, Round Rock, TX (US);

Sanjeev Ghai, Round Rock, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/34 (2018.01); G06F 9/54 (2006.01); G06F 12/0811 (2016.01); G06F 9/30 (2018.01); G06F 9/52 (2006.01); G06F 12/0842 (2016.01); G06F 12/0891 (2016.01); G06F 12/0888 (2016.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3834 (2013.01); G06F 9/30043 (2013.01); G06F 9/34 (2013.01); G06F 9/544 (2013.01); G06F 12/0811 (2013.01); G06F 2212/283 (2013.01);
Abstract

A data processing system includes multiple processing units all having access to a shared memory. A processing unit of the data processing system includes a processor core including an upper level cache, core reservation logic that records addresses in the shared memory for which the processor core has obtained reservations, and an execution unit that executes memory access instructions including a fronting load instruction. Execution of the fronting load instruction generates a load request that specifies a load target address. The processing unit further includes lower level cache that, responsive to receipt of the load request and based on the load request indicating an address match for the load target address in the core reservation logic, protects the load target address against access by any conflicting memory access request during a protection interval following servicing of the load request.


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