The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Oct. 08, 2018
Applicant:

Zkw Group Gmbh, Wieselburg, AT;

Inventor:

Erik Edlinger, Vienna, AT;

Assignee:

ZKW Group GmbH, Wieselburg, AT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/00 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/34 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0206 (2013.01); H05K 1/113 (2013.01); H05K 3/0094 (2013.01); H05K 3/3452 (2013.01); H05K 1/112 (2013.01); H05K 3/42 (2013.01); H05K 2201/09481 (2013.01); H05K 2201/09563 (2013.01); H05K 2201/09572 (2013.01); H05K 2201/09609 (2013.01); H05K 2201/09627 (2013.01); H05K 2201/09636 (2013.01); H05K 2203/043 (2013.01); H05K 2203/045 (2013.01); H05K 2203/0455 (2013.01); H05K 2203/1476 (2013.01);
Abstract

In a printed circuit board (), thermal vias () are formed between the lower surface (A) and an upper surface (B) of the substrate plate () of the printed circuit board through the steps of: applying a respective solder resist mask () to the lower surface (A) and the upper surface (B); applying solder to the lower surface (A) and reflow soldering the solder, wherein the solder penetrates into the boreholes () and forms convex menisci () protruding beyond the edge () of the respective boreholes on the lower surface (A); and creating regions () on the upper surface (B), which are freed from solder resist material, and which are intended for contacting at least one electronic component () on the upper surface and each of which comprise at least one of the thermal vias. Subsequently, the upper surface (B) can be provided with electrical components () on these regions (). The first solder resist mask () has a respective region () that is free of solder resist on the lower surface around the edge of every borehole ().


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