The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Sep. 11, 2018
Applicant:

National Institute of Advanced Industrial Science and Technology, Tokyo, JP;

Inventors:

Hiroyuki Ota, Ibaraki, JP;

Shinji Migita, Ibaraki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/088 (2006.01); H01L 27/1159 (2017.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78391 (2014.09); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H01L 23/53266 (2013.01); H01L 27/0886 (2013.01); H01L 27/1159 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/40111 (2019.08); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Power consumption of a semiconductor device is reduced by sharpening the rise of a drain current when a gate voltage of a field effect transistor is less than a threshold voltage. As means therefor, in a fully-depleted MOSFET in which a thickness of a semiconductor layer serving as a channel region is 20 nm or less, a gate plug connected to a gate electrode is constituted of a first plug, a ferroelectric film, and a second plug sequentially stacked on the gate electrode. Here, an area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than an area where the gate electrode and a semiconductor layer serving as an active region overlap.


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