The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Oct. 23, 2020
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Shunsuke Isono, Osaka, JP;

Hidenari Kanehara, Kyoto, JP;

Sanshiro Shishido, Osaka, JP;

Takeyoshi Tokuhara, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/30 (2006.01); H04N 5/374 (2011.01); H04N 5/376 (2011.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/307 (2013.01); H01L 27/14605 (2013.01); H01L 27/14607 (2013.01); H01L 27/14636 (2013.01); H01L 27/14665 (2013.01); H04N 5/374 (2013.01); H04N 5/376 (2013.01); H01L 27/14603 (2013.01); H01L 27/14612 (2013.01); H01L 27/14621 (2013.01); H01L 27/14623 (2013.01); H01L 27/14627 (2013.01); H01L 27/14643 (2013.01);
Abstract

An imaging device including a semiconductor substrate including a pixel region and a peripheral region; an insulating layer covering the pixel and peripheral regions; first electrodes located on the insulating layer above the pixel region; a photoelectric conversion layer covering the first electrodes; a second electrode that covers the photoelectric conversion layer; detection circuitry electrically connected to the first electrodes; peripheral circuitry electrically connected to the detection circuitry, and; and a third electrode located on the insulating layer. The second electrode includes a connection region in which the second electrode is connected to third electrode, the connection region overlaps analog circuitry in a plan view, and in any cross-sections perpendicular to a surface of the semiconductor substrate and parallel to a column or row direction and that intersects at least one of the first electrodes, the digital circuitry includes no transistor that is located directly below the connection region.


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