The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

May. 24, 2017
Applicant:

Soitec, Bernin, FR;

Inventors:

Bich-Yen Nguyen, Austin, TX (US);

Ludovic Ecarnot, Vaulnaveys-le-Haut, FR;

Nadia Ben Mohamed, Echirolles, FR;

Christophe Malville, Lumbin, FR;

Assignee:

Soitec, Bernin, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/568 (2013.01); H01L 21/4857 (2013.01); H01L 21/78 (2013.01);
Abstract

A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer; assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.


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