The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Sep. 05, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Atsushi Okuyama, Yokohama Kanagawa, JP;

Yoshihiko Kamata, Yokohama Kanagawa, JP;

Hiromitsu Komai, Kamakura Kanagawa, JP;

Takuyo Kodama, Sagamihara Kanagawa, JP;

Yuki Ishizaki, Yokohama Kanagawa, JP;

Yoko Deguchi, Yokohama Kanagawa, JP;

Hiroyuki Kaga, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/26 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a bit line electrically connected to a memory cell, a first node electrically connected to the bit line, a first driver configured to increase a voltage of the first node to a first voltage, a first buffer circuit configured to store data based on the voltage of the first node, a bus electrically connected to the first buffer circuit, a first transistor electrically connected between the first node and the bus, and a second buffer circuit electrically connected to the bus. The first buffer circuit is electrically connected to an input terminal of the first driver. The first driver changes a voltage of the bus based on the data stored in the first buffer circuit.


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