The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Jan. 21, 2020
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventors:

Eric Hunt-Schroeder, Essex Junction, VT (US);

Alexander J. Filmer, Whitesboro, NY (US);

Assignee:

MARVELL ASIA PTE, LTD., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G05F 1/567 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G05F 1/567 (2013.01); G11C 5/14 (2013.01);
Abstract

Disclosed are embodiments of an integrated circuit (IC) chip that includes an on-chip parameter generation system. The system includes multiple parameter generators (e.g., voltage generators, current generators, capacitance generators, etc.) and an integrated calibration circuit. The calibration circuit is configured to automatically, sequentially, and repeatedly calibrate the parameter generators in order to minimize chip-to-chip variations in parameters supplied to other on-chip components under real world operating conditions throughout the life of the IC chip. In other words, the integrated calibration circuit effectively minimizes temperature-induced chip-to-chip variations, age-induced chip-to-chip variations, etc. in parameters generated by the on-chip parameter generators. Also disclosed herein are embodiments of an associated method.


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