The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Feb. 26, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Jacco van Oevelen, Niederaichbach, DE;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); H02M 3/158 (2006.01); H02M 1/32 (2007.01); G01R 31/3193 (2006.01); G01R 31/319 (2006.01); G01R 31/3187 (2006.01); G01R 31/34 (2020.01);
U.S. Cl.
CPC ...
G01R 31/31724 (2013.01); G01R 31/3187 (2013.01); G01R 31/31721 (2013.01); G01R 31/31924 (2013.01); G01R 31/31932 (2013.01); G01R 31/31937 (2013.01); H02M 1/32 (2013.01); H02M 3/1582 (2013.01);
Abstract

Built-in self-test (BIST) circuits and related methods are disclosed. An example BIST circuit includes a state machine to generate a control signal to reduce a gate voltage associated with a transistor from a first voltage to a second voltage when an enable signal is asserted, the transistor to be enabled at the first voltage and the second voltage, and assert an alert signal when a gate-to-source voltage associated with the transistor satisfies a threshold when the gate voltage is reduced to the second voltage.


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Quick Actions:

van Oevelen, Jacco. (2021). Built-in self-test circuits and related methods (U.S. Patent No. 11112455). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11112455

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