The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Oct. 31, 2018
Applicant:

Keysight Technologies, Inc., Santa Rosa, CA (US);

Inventors:

Pradosh Tapan Datta, Kolkata, IN;

Tanuman Bhaduri, Kolkata, IN;

Kingshuk Mandal, Kolkata, IN;

Alon Regev, Woodland Hills, CA (US);

James Robert Bauder, Chatsworth, CA (US);

Assignee:

Keysight Technologies, Inc., Santa Rosa, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/26 (2006.01); H04L 12/24 (2006.01); H04L 12/801 (2013.01); H04L 12/851 (2013.01); H04L 12/939 (2013.01); H04L 12/861 (2013.01); H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
H04L 43/50 (2013.01); H04L 41/145 (2013.01); H04L 43/0823 (2013.01); H04L 43/12 (2013.01); H04L 47/245 (2013.01); H04L 47/34 (2013.01); H04L 49/552 (2013.01); H04L 49/555 (2013.01); H04L 49/9057 (2013.01); H04L 69/166 (2013.01);
Abstract

Methods, systems, and computer readable media for testing effects of simulated frame preemption and deterministic fragmentation of preemptable frames in a frame-preemption-capable network are disclosed. According to one method, a device under test including at least one processor simulates frame preemption by generating a plurality of simulated preempted frame fragments and an express frame. The test device deterministically orders, independently from MAC merge sublayer fragmentation and ordering, the simulated preempted frame fragments and the express frame for transmission to the DUT. The test device transmits the simulated preempted frame fragments and the express frame to the DUT in an order corresponding to the deterministic ordering. The test device receives a response of the DUT to the simulated preempted frame fragments and the express frame. The test device determines, based on the response of the DUT, whether the DUT operates in accordance with specifications for frame preemption.


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