The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2021
Filed:
Apr. 30, 2019
Xilinx, Inc., San Jose, CA (US);
Garik Mkrtchyan, Fremont, CA (US);
Satish Sivaswamy, Fremont, CA (US);
Jinny Singh, San Jose, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Some examples described herein relate to routing in routing elements (e.g., switches). In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network among switches interconnected in an array of data processing engines (DPEs), generate routes for an application on the modeled communication network, and translate the routes to a file. Each DPE includes a hardened processor core, a memory module, and one or more of the switches. Each switch includes an input or output port that is capable of being shared by multiple routes. Port(s) of each switch are modeled as respective node(s). Generating the routes includes using an A* algorithm that includes a congestion costing function based on a capacity of respective nodes in the modeled communication network and a cumulative demand for the respective nodes.