The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Dec. 06, 2017
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Yusuke Kaji, Chiyoda-ku, JP;

Hodaka Rokubuichi, Chiyoda-ku, JP;

Satoshi Kondo, Chiyoda-ku, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H02M 7/00 (2006.01); H02M 7/5387 (2007.01); H01L 23/14 (2006.01); H02P 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 23/49838 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 25/072 (2013.01); H02M 7/003 (2013.01); H02M 7/53871 (2013.01); H01L 23/142 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01); H02P 27/08 (2013.01);
Abstract

A semiconductor device includes an insulating substrate, a semiconductor element, a conductor substrate, and a case member. The semiconductor element is connected above the insulating substrate, and the conductor substrate is connected above the semiconductor element. The case member surrounds a region overlapping with the insulating substrate, the semiconductor element, and the conductor substrate in plan view to avoid the region. A plurality of metal patterns are arranged on a main surface of an insulating layer. A groove is formed between a pair of adjacent metal patterns of the plurality of metal patterns. A through hole is formed in the conductor substrate at a position overlapping with the groove in plan view.


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