The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Dec. 24, 2019
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Mi-Hyun Hwang, Seoul, KR;

Jong-Chern Lee, Chungcheongbuk-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 7/00 (2006.01); G11C 29/02 (2006.01); G11C 29/00 (2006.01); G11C 7/10 (2006.01); G11C 29/24 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/025 (2013.01); G11C 7/1012 (2013.01); G11C 7/1039 (2013.01); G11C 29/24 (2013.01); G11C 29/44 (2013.01); G11C 29/702 (2013.01);
Abstract

Disclosed are a memory device and an operating method thereof, and the memory device includes a plurality of first data lines, a plurality of second data lines, a common redundant memory region coupled to at least one repair line of the second data lines, a plurality of normal memory regions coupled to the first data lines in common, and coupled in common to the remaining the second data lines excluding the repair line, and a repair circuit coupled to the first and second data lines, and suitable for replacing at least one defective memory cell in the normal memory regions with at least one redundant memory cell in the common redundant memory region by shifting some or all of the first data lines to some or all of the second data lines, based on a row address, a column address and a region address.


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