Semiconductor memory device

Abstract

A semiconductor memory device includes a word line connected to memory cells, bit lines respectively connected to the memory cells, and a control circuit configured to control voltages applied to the word line and the bit lines during a write operation. When writing data into a target memory cell, the control circuit executes first and second loops in sequence. In executing the first loop, the control circuit applies a first program voltage to the word line during the program operation, and applies a verify voltage to the word line during the verify operation, and upon detecting that the verify operation neither passed nor failed, the control circuit selects one of two pass write voltages to be applied to the bit line connected to the target memory cell during the program operation of the second loop according to a sequential position of the first loop in the sequence of loops.