Gate driving circuit and display device using the same

Abstract

A gate driving circuit and a display device are disclosed. The gate driving circuit includes a shift register including a plurality of stages. Among the stages, an Nth stage includes a first transistor charging a Q node and a junction stress control circuit. A pull-up transistor using the Q node as a gate input controls an output signal of a stage output terminal. The junction stress control circuit includes a first, second, and third control transistors. The first control transistor, the second control transistor, the third control transistor, and the first transistor are connected to each other through a common node. The second control transistor adjusts junction stresses for the first control transistor and the first transistor by controlling a voltage of the common node. When the second control transistor is turned off, the third control transistor discharges the voltage of the common node.