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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11107176 B1

PDFFull Text
Date of Patent:
Aug. 31, 2021

Filed:

Oct. 01, 2013

Scheduling cache traffic in a tile-based architecture

Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Ziyad S. Hakura, Gilroy, CA (US);

Rouslan Dimitrov, San Carlos, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:

Artegis Law Group, LLP

Primary Examiner:

Ryan McCulley

Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06T 15/20 (2011.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01); G06F 12/0875 (2016.01); G06T 15/40 (2011.01); G06F 9/38 (2018.01); G09G 5/395 (2006.01); G09G 5/00 (2006.01); G06T 15/50 (2011.01); G06F 12/0808 (2016.01); G06F 9/44 (2018.01); G06T 15/80 (2011.01); G06T 17/20 (2006.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 9/38 (2013.01); G06F 9/44 (2013.01); G06F 12/0808 (2013.01); G06F 12/0875 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06T 15/405 (2013.01); G06T 15/503 (2013.01); G06T 15/80 (2013.01); G06T 17/20 (2013.01); G09G 5/003 (2013.01); G09G 5/395 (2013.01); G06F 2212/302 (2013.01); Y02D 10/00 (2018.01);
Abstract

A tile-based system for processing graphics data. The tile based system includes a first screen-space pipeline, a cache unit, and a first tiling unit. The first tiling unit is configured to transmit a first set of primitives that overlap a first cache tile and a first prefetch command to the first screen-space pipeline for processing, and transmit a second set of primitives that overlap a second cache tile to the first screen-space pipeline for processing. The first prefetch command is configured to cause the cache unit to fetch data associated with the second cache tile from an external memory unit. The first tiling unit may also be configured to transmit a first flush command to the screen-space pipeline for processing with the first set of primitives. The first flush command is configured to cause the cache unit to flush data associated with the first cache tile.

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