The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Mar. 09, 2021
Applicants:

Henry Verheyen, Marina, CA (US);

Jianjun Wen, San Jose, CA (US);

Inventors:

Henry Verheyen, Marina, CA (US);

Jianjun Wen, San Jose, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G06F 5/01 (2006.01); G06F 7/523 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 5/01 (2013.01); G06F 7/523 (2013.01); G06F 9/5027 (2013.01);
Abstract

A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.


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