The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Sep. 04, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

David Wolpert, Poughkeepsie, NY (US);

Timothy A. Schell, Cary, NC (US);

Erwin Behnen, Austin, TX (US);

Leon Sigal, Monsey, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/30 (2020.01);
Abstract

Methods, systems and computer program products for providing flexible constraint-based logic cell placement are provided. Aspects include determining a cell placement restriction rule that specifies an offset requirement between a first type of logic cell and a second type of logic cell. Responsive to placing a first cell that is the first type of logic cell within a semiconductor layout, aspects include tagging the first cell with the cell placement restriction rule. Aspects also include placing a second cell that is the second type of logic cell at an initial position within the semiconductor layout. Responsive to determining that the initial position of the second cell violates the cell placement restriction rule, aspects include repositioning the first cell or the second cell to a modified position within the semiconductor layout such that the modified position satisfies the cell placement restriction rule.


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