The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Dec. 20, 2018
Applicant:

Universita' Degli Studi Di Napoli Federico Ii, Napoli, IT;

Inventor:

Raffaele Giordano, Pozzuoli, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/34 (2020.01); H03K 19/177 (2020.01); G06F 30/343 (2020.01); G01R 31/3181 (2006.01); G06F 30/337 (2020.01); G06F 30/347 (2020.01); G06F 119/06 (2020.01);
U.S. Cl.
CPC ...
G06F 30/34 (2020.01); G01R 31/31816 (2013.01); G06F 30/343 (2020.01); H03K 19/177 (2013.01); G06F 30/337 (2020.01); G06F 30/347 (2020.01); G06F 2119/06 (2020.01);
Abstract

A method for generating redundant configuration in FPGA devices includes: analysing the configuration pertaining to a given design to be configured, or already configured, in the FPGA device, in order to identify programmed and empty configuration memory portions, configuring the FPGA device for implementing said design, measuring the power consumption of the configured FPGA device, copying the configuration from at least some subsets of the programmed portion to subsets of the empty portion, (a) verifying the configuration read back from said subsets of the empty portion with the configuration data read from said subsets of the programmed portion, (b) verifying whether the functionality of the design after the copy is still correct, (c) measuring the power consumption of the FPGA device, and verifying whether the power consumption of the FPGA device after the copy is acceptable according to pre-defined criteria, if the verification steps (a), (b) and (c) are all successful the redundant configuration is correctly generated, and if the verification steps (a), (b) and (c) are not all successful the method restarts from the beginning choosing other subsets of the empty portion of the FPGA device for hosting the configuration data from said subsets of the programmed portion.


Find Patent Forward Citations

Loading…