The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

May. 01, 2019
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventor:

Anh Dinh Luong, Austin, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/78 (2006.01); G06F 13/40 (2006.01); G06F 13/38 (2006.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 15/7871 (2013.01); G06F 9/4401 (2013.01); G06F 9/4411 (2013.01); G06F 13/385 (2013.01); G06F 13/4081 (2013.01);
Abstract

A method is provided to generate a configuration descriptor for a chipset in a computing unit. The method includes determining, by one or more processors, a plurality of desired interface configurations for the chipset and for each of the one or more desired interface configurations, determining one or more ports of the chipset and corresponding platform connectors that satisfy features of the each of the one or more of the desired interface configurations based on a chipset description and a platform description. The method further includes assigning a port from among the determined one or more ports to the each of the one or more of the desired interface configurations and generating a chipset configuration descriptor based on the assigning of ports to each of the one or more desired interface configurations. In some embodiments, the chipset is initialized based on the configuration descriptor.


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