The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Jul. 29, 2016
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Aaron L. Smith, Seattle, WA (US);

Jan S. Gray, Bellevue, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 15/78 (2006.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3836 (2013.01); G06F 9/3005 (2013.01); G06F 9/3016 (2013.01); G06F 9/3017 (2013.01); G06F 9/30181 (2013.01); G06F 9/30185 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/3834 (2013.01); G06F 9/3838 (2013.01); G06F 9/3855 (2013.01); G06F 9/3873 (2013.01); G06F 9/3885 (2013.01); G06F 9/3889 (2013.01); G06F 9/3897 (2013.01); G06F 12/0875 (2013.01); G06F 15/7867 (2013.01);
Abstract

Apparatus and methods are disclosed for implementing incremental schedulers for out-of-order block-based processors, including field programmable gate array implementations. In one example of the disclosed technology, a processor includes an instruction scheduler formed by configuring one or more look up table RAMs to store ready state data for a plurality of instructions in an instruction block. The instruction scheduler further includes a plurality of queues that store ready state data for the processor and sends dependency information to ready determination logic on a first in/first out basis. The instruction scheduler selects one or more of the ready instructions to be issued and executed by the block-based processor.


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