The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Feb. 22, 2020
Applicant:

Dinoplusai Holdings Limited, Fremont, CA (US);

Inventors:

Yutian Feng, San Jose, CA (US);

Yujie Hu, Fremont, CA (US);

Assignee:

DINOPLUSAI HOLDINGS LIMITED, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/53 (2006.01); G06F 7/485 (2006.01); G06F 7/50 (2006.01); G06F 7/501 (2006.01);
U.S. Cl.
CPC ...
G06F 7/5312 (2013.01); G06F 7/485 (2013.01); G06F 7/50 (2013.01); G06F 7/501 (2013.01); G06F 7/5318 (2013.01);
Abstract

A computing device to implement fast floating-point adder tree for the neural network applications is disclosed. The fast float-point adder tree comprises a data preparation module, a fast fixed-point Carry-Save Adder (CSA) tree, and a normalization module. The floating-point input data comprises a sign bit, exponent part and fraction part. The data preparation module aligns the fraction part of the input data and prepares the input data for subsequent processing. The fast adder uses a signed fixed-point CSA tree to quickly add a large number of fixed-point data into 2 output values and then uses a normal adder to add the 2 output values into one output value. The fast adder uses for a large number of operands is based on multiple levels of fast adders for a small number of operands. The output from the signed fixed-point Carry-Save Adder tree is converted to a selected floating-point format.


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