The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Jul. 22, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Robert Callaghan Taft, Munich, DE;

Vineethraj Rajappan Nair, Freising, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); G06F 1/10 (2006.01); H03L 7/099 (2006.01); H03K 5/00 (2006.01); H03K 3/03 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); H03K 3/0315 (2013.01); H03K 5/00006 (2013.01); H03L 7/0995 (2013.01);
Abstract

An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.


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