The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Sep. 13, 2019
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventor:

Thomas Saroshan David, Lakeway, TX (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); H03K 17/6871 (2013.01); H03K 2217/0054 (2013.01);
Abstract

A configurable clock buffer including first and second buffers and isolation circuitry. The first buffer has an input coupled to a clock input node and has an output coupled to a clock output node. The second buffer has an input coupled to an intermediate input node and has an output coupled to an intermediate output node. The isolation circuitry is responsive to at least one mode signal, in which it electrically couples the intermediate input node to the clock input node and electrically couples the intermediate output node to the clock output node when the at least one mode signal is in a first state, and in which it electrically couples the intermediate input node to a static node and electrically isolates the intermediate output node from the clock output node when the at least one mode signal is in a second state.


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