The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Aug. 22, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Steve Edward Harrell, Corinth, TX (US);

Keith Eric Sanborn, Tucson, AZ (US);

Wai Lee, Dallas, TX (US);

Erika Lynn Mazotti, San Martin, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 23/525 (2006.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/00 (2013.01); H01L 23/5258 (2013.01); H01L 27/0802 (2013.01); H01L 28/20 (2013.01);
Abstract

An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression.


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