The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Sep. 29, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Sang-Uk Kim, Cheonan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 23/49816 (2013.01); H01L 25/50 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1047 (2013.01); H01L 2225/1082 (2013.01);
Abstract

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a first semiconductor chip on a first substrate, a first molding layer covering a sidewall of the first semiconductor chip and including at least two guide holes that expose the first substrate and are spaced apart from each other in a periphery of the first substrate, a second substrate on the first molding layer, a connection terminal between the first substrate and the second substrates and connecting the first and second substrates to each other, and an alignment structure that extends from a bottom surface of the second substrate into each of the at least two guide holes of the first molding layer. A height of the alignment structure is greater than a height of the first molding layer and the first semiconductor chip.


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