The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Sep. 27, 2018
Applicant:

Wuhan China Star Optoelectronics Technology Co., Ltd., Wuhan, CN;

Inventors:

Chunpeng Guo, Wuhan, CN;

Yingchi Wang, Wuhan, CN;

Chunhung Huang, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 27/12 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); G02F 1/1345 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); H01L 24/83 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 27/124 (2013.01); G02F 1/13458 (2013.01); H01L 23/544 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/06155 (2013.01); H01L 2224/06177 (2013.01); H01L 2224/8313 (2013.01); H01L 2224/83851 (2013.01);
Abstract

The invention provides an array substrate and chip bonding method, the array substrate comprising: an active area, and a bonding area located around the active area, wherein the bonding area is provided with an input terminal group, a first output terminal group and a second output terminal a group; the first output terminal group is located at a side of the input terminal group away from the active area, and the second output terminal group is located between the first output terminal group and the input terminal group; when bonding chips, the first output terminal group or the second output terminal group is selected to cooperate with the input terminal group for chip bonding according to the chip type. By simultaneously providing the first and second output terminal groups, the bonding of the second type chip increases the distance between the chip and the edge of the array substrate.


Find Patent Forward Citations

Loading…