The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2021
Filed:
Feb. 09, 2017
Applicant:
Mitsubishi Electric Corporation, Tokyo, JP;
Inventors:
Hiroyuki Harada, Tokyo, JP;
Naoki Yoshimatsu, Tokyo, JP;
Osamu Usui, Tokyo, JP;
Yuji Imoto, Tokyo, JP;
Yuki Yoshioka, Tokyo, JP;
Assignee:
Mitsubishi Electric Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/057 (2006.01); H01L 23/047 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/24 (2006.01); H01L 23/373 (2006.01); H01L 23/36 (2006.01); H01L 23/28 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01); H02P 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/047 (2013.01); H01L 23/3142 (2013.01); H01L 23/4951 (2013.01); H01L 23/4952 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 23/49575 (2013.01); H02P 27/08 (2013.01);
Abstract
A semiconductor chip () is disposed on the insulation substrate (). A lead frame () is bonded to an upper surface of the semiconductor chip (). A sealing resin () covers the semiconductor chip (), the insulation substrate (), and the lead frame (). A stress mitigation resin () having a lower elastic modulus than that of the sealing resin () is partially applied to an end of the lead frame ().