The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Sep. 26, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hassan Naser, Austin, TX (US);

Calist Friedman, Austin, TX (US);

Matthew A. Cooke, Cedar Park, TX (US);

Daniel L. Stasiak, Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/48 (2006.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01L 21/76894 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5258 (2013.01); H01L 28/10 (2013.01);
Abstract

An approach to creating a semiconductor chip including a semiconductor substrate with one or more topside metal layers and one or more backside metal layers. The approach creates the semiconductor chip with one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate and one or more inductors in the one or more backside metal layer. Furthermore, the approach creates the semiconductor chip with one or more through silicon vias extending through the semiconductor substrate connecting the one or more inductors in the one or more backside metal layers and the one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate.


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