The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Jun. 02, 2017
Applicant:

Surecore Limited, Leeds, GB;

Inventors:

Stefan Cosemans, Leeds, GB;

Bram Rooseleer, Leeds, GB;

Assignee:

Surecore Limited, Leeds, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 11/4094 (2006.01); G11C 5/14 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 5/145 (2013.01); G11C 11/4074 (2013.01); G11C 11/4087 (2013.01); G11C 2207/005 (2013.01);
Abstract

There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.


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