The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Sep. 26, 2019
Applicant:

Arm Limited, Cambridge, GB;

Inventor:

Simon John Craske, Cambridge, GB;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1441 (2013.01); G06F 12/0292 (2013.01); G06F 12/14 (2013.01); G06F 12/145 (2013.01); G06F 12/1433 (2013.01); G06F 12/1458 (2013.01); G06F 12/1483 (2013.01);
Abstract

An apparatus and method are provided for performing data processing operations. The apparatus has processing circuitry for performing data processing operations configured to operate in a normal mode and a memory region management mode. A memory is used to store data accessed by the processing circuitry when performing the data processing operations. A memory region table is provided to define accessibility control information for each of a number of memory regions within the memory. An access control mechanism controls access to the memory in response to an access request issued by the processing circuitry, and a memory protection unit providing a bypass indication for one or more memory regions is referenced by the access control mechanism when the processing circuitry is in the memory region management mode. The access control mechanism is arranged to constrain access to the memory location identified by the access request based on the accessibility control information defined in the memory region management mode when the processing circuitry is operating in the normal mode. When the processing circuitry is operating in the memory region management mode, the access control mechanism is arranged to reference the memory protection unit and when the bypass indication is set for the memory region, to process the access to the memory location unconstrained by the memory region table.


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